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ST
Sitronix
OVERVIEW
The ST7522 family of dot matrix LCD drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM. The drivers are available in two configurations The ST7522 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages. These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems. The ST7522 which is able to drive 1 line of 6 Chinese characters or 2 lines of 12 Chinese characters each line with two ST7522.
ST7522
17 x 96 Dot Matrix LCD Controller/Driver
FEATURES
Fast 8-bit MPU interface compatible with 80- and 68- family microcomputers and serial interface Clock synchronous serial interface Many command set Display data Read/Write, display ON/OFF, Normal/Reverse display mode, page address set , column address set , status read , display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, adjustable OSC frequency, booster input voltage select, follower input voltage and amplified ratio selectable 4 static indicator and 96 icon available Total 118 (segment + common + static) drive sets Wide range of supply voltages VDD - VSS2.7 to 5.5 V VDD - V53.5 to 7.0 V VDD - VCAP3 3.5 to 7.0 V Low-power CMOS 64 level digital contrast control
Product name
Clock frequency On-Chip External 2.8KHz
Number Number of COM of SEG 17 96
Bias
Duty
ST7522D 1.2KHz,2.4KHz (When VDD=3.0V)
1/5,1/6 1/17,1/33
Ver 1.0c
1/45
2002/07/10
ST7522
ST7522 Serial Specification Revision History Version 1.0 1.0a 1.0b Date Description
2002/01/30 New specification version 2002/02/20 Modify cover page's product name 2002/03/18 Adding FR frequency for "OSC frequency set" command 1. 2. Adding "Slave chip notice" in application circuit Adding "Software example" Adding "Follower-contrast curve" Adding "Master mode application circuit" Adding "I/O pad configuration"
1.0c
2002/07/10 3. 4. 5.
Ver 1.0c
2/45
2002/07/10
ST7522
BLOCK DIAGRAM
V1,V2,V3,V4,V5 COM0~COM15 COMI SEG0~SEG95 S1~S4 COMS
VDD
LCD driver circuit
Common counter
Display data latch circuit
Display start line register
Line address decoder
Line counter
Display data RAM (96 X33 bits)
Column address decoder Column address counter Column address register Low-address register Bus holder CL CLS FR
CAP1 CAP2 CAP3
Display timing generator circuit
Power circuit
Command decoder
Status
MPU interface
D0~D7
P/S
M/S
/CS1,CS2
Ver 1.0c
3/45
/WR,/RD
/RES
C86
A0
I/O buffer
VSS
2002/07/10
ST7522
PAD ARRANGEMENT
Chip specifications of AL pad package Chip size : 3720 m x 5040 m Minimum pad pitch : 110m Pad size : 90m X 90m
SEG57/SEG74 SEG58/SEG75 SEG59/SEG76 SEG60/SEG77 SEG61/SEG78 SEG62/SEG79 SEG63/SEG80 SEG64/SEG81 SEG65/SEG82 SEG66/SEG83 SEG67/SEG84 SEG68/SEG85 SEG69/SEG86 SEG70/SEG87 SEG71/SEG88 SEG72/SEG89 SEG73/SEG90 SEG74/SEG91 SEG75/SEG92 SEG76/SEG93 SEG77/SEG94 SEG78/SEG95 SEG79/COMI SEG80/COM15 SEG81/COM14 SEG82/COM13 SEG83/COM12 SEG84/COM11 SEG85/COM10 SEG86/COM9 SEG73/SEG56 SEG72/SEG55 SEG71/SEG54 SEG70/SEG53 SEG69/SEG52 SEG68/SEG51 SEG67/SEG50 SEG66/SEG49 SEG65/SEG48 SEG64/SEG47 SEG63/SEG46 SEG62/SEG45 SEG61/SEG44 SEG60/SEG43 SEG59/SEG42 SEG58/SEG41 SEG57/SEG40 SEG56/SEG39 SEG55/SEG38 SEG54/SEG37 SEG53/SEG36 SEG52/SEG35 SEG51/SEG34 SEG50/SEG33 SEG49/SEG32 SEG48/SEG31 SEG47/SEG30 SEG46/SEG29 SEG45/SEG28 SEG44/SEG27 SEG43/SEG26 SEG42/SEG25 SEG41/SEG24 SEG40/SEG23 SEG39/SEG22 SEG38/SEG21 SEG37/SEG20 SEG36/SEG19 SEG35/SEG18 SEG34/SEG17 SEG33/SEG16 SEG32/SEG15 SEG31/SEG14 SEG30/SEG13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75
SEG87/ COM8 SEG88/ COM7 SEG89/ COM6 SEG90/ COM5 SEG91/ COM4 SEG92/ COM3 SEG93/ COM2 SEG94/ COM1 SEG95/ COM0 CAP3 CAP2 CAP1 V2 V5 M/S V3 V4 V1 FR CLS RES C86 VDD R/W A0 E(RD) CS2 /CS1 D7 D6 D5 D4 D3 D2 D1 D0 VSS CL P/S S4 S3 S2 S1 COMS
* Substrate connect to VDD.
Ver 1.0c 4/45 2002/07/10
COM0/SEG0 COM1/SEG1 COM2/SEG2 COM3/SEG3 COM4/SEG4 COM5/SEG5 COM6/SEG6 COM7/SEG7 COM8/SEG8 COM9/SEG9 COM10/SEG10 COM11/SEG11 COM12/SEG12 COM13/SEG13 COM14/SEG14 COM15/SEG15 COMI/SEG16 SEG0/SEG17 SEG1/SEG18 SEG2/SEG19 SEG3/SEG20 SEG4/SEG21 SEG5/SEG22 SEG6/SEG23 SEG7/SEG24 SEG8/SEG25 SEG9/SEG26 SEG10/SEG27 SEG11/SEG28 SEG12/SEG29
ST7522
PAD CENTER COORDINATES
(chip size : 3720 m x 5040 m)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Pin Name Master Slave SEG56 SEG73 SEG55 SEG72 SEG54 SEG71 SEG53 SEG70 SEG52 SEG69 SEG51 SEG68 SEG50 SEG67 SEG49 SEG66 SEG48 SEG65 SEG47 SEG64 SEG46 SEG63 SEG45 SEG62 SEG44 SEG61 SEG43 SEG60 SEG42 SEG59 SEG41 SEG58 SEG40 SEG57 SEG39 SEG56 SEG38 SEG55 SEG37 SEG54 SEG36 SEG53 SEG35 SEG52 SEG34 SEG51 SEG33 SEG50 SEG32 SEG49 SEG31 SEG48 SEG30 SEG47 SEG29 SEG46 SEG28 SEG45 SEG27 SEG44 SEG26 SEG43 SEG25 SEG42 SEG24 SEG41 SEG23 SEG40 SEG22 SEG39 SEG21 SEG38 SEG20 SEG37 SEG19 SEG36 SEG18 SEG35 SEG17 SEG34 SEG16 SEG33 SEG15 SEG32 SEG14 SEG31 SEG13 SEG30 SEG12 SEG29 SEG11 SEG28 SEG10 SEG27 SEG9 SEG26 SEG8 SEG25 X -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1745 -1615 -1495 -1375 -1265 -1155 Y 2405 2275 2155 2035 1925 1815 1705 1595 1485 1375 1265 1155 1045 935 825 715 605 495 385 275 165 55 -55 -165 -275 -385 -495 -605 -715 -825 -935 -1045 -1155 -1265 -1375 -1485 -1595 -1705 -1815 -1925 -2035 -2155 -2275 -2405 -2405 -2405 -2405 -2405 -2405 Pad No. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Pin Name X Master Slave SEG7 SEG24 -1045 SEG6 SEG23 -935 SEG5 SEG22 -825 SEG4 SEG21 -715 SEG3 SEG20 -605 SEG2 SEG19 -495 SEG1 SEG18 -385 SEG0 SEG17 -275 COMI SEG16 -165 COM15 SEG15 -55 COM14 SEG14 55 COM13 SEG13 165 COM12 SEG12 275 COM11 SEG11 385 COM10 SEG10 495 COM9 SEG9 605 COM8 SEG8 715 COM7 SEG7 825 COM6 SEG6 935 COM5 SEG5 1045 COM4 SEG4 1155 COM3 SEG3 1265 COM2 SEG2 1375 COM1 SEG1 1495 COM0 SEG0 1615 COMS 1745 S1 1745 S2 1745 S3 1745 S4 1745 P/S 1745 CL 1745 VSS 1745 D0 1745 D1 1745 D2 1745 D3 1745 D4 1745 D5 1745 D6 1745 D7 1745 /CS1 1745 CS2 1745 E(RD) 1745 A0 1745 R/W 1745 VDD 1745 C86 1745 RES 1745 Y -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2405 -2275 -2155 -2035 -1925 -1815 -1705 -1595 -1485 -1375 -1265 -1155 -1045 -935 -825 -715 -605 -495 -385 -275 -165 -55 55 165 Pad No. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Pin Name Master Slave CLS FR V1 V4 V3 M/S V5 V2 CAP1 CAP2 CAP3 SEG95 COM0 SEG94 COM1 SEG93 COM2 SEG92 COM3 SEG91 COM4 SEG90 COM5 SEG89 COM6 SEG88 COM7 SEG87 COM8 SEG86 COM9 SEG85 COM10 SEG84 COM11 SEG83 COM12 SEG82 COM13 SEG81 COM14 SEG80 COM15 SEG79 COMI SEG78 SEG95 SEG77 SEG94 SEG76 SEG93 SEG75 SEG92 SEG74 SEG91 SEG73 SEG90 SEG72 SEG89 SEG71 SEG88 SEG70 SEG87 SEG69 SEG86 SEG68 SEG85 SEG67 SEG84 SEG66 SEG83 SEG65 SEG82 SEG64 SEG81 SEG63 SEG80 SEG62 SEG79 SEG61 SEG78 SEG60 SEG77 SEG59 SEG76 SEG58 SEG75 SEG57 SEG74 X 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1745 1615 1495 1375 1265 1155 1045 935 825 715 605 495 385 275 165 55 -55 -165 -275 -385 -495 -605 -715 -825 -935 -1045 -1155 -1265 -1375 -1495 -1615 Y 275 385 495 605 715 825 935 1045 1155 1265 1375 1485 1595 1705 1815 1925 2035 2155 2275 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405 2405
Ver 1.0c
5/45
2002/07/10
ST7522
PIN DESCRIPTION
(1) Power Pins
Name
VDD VSS CAP1~3 V1~V5
I/O
-
Description
Connected to the +5V 0r +3V dc power. Common to the Vcc MPU power pin. 0V dc pin connected to the system ground. Capacitor connector pin for voltage booster Multi-level power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. These voltages must satisfy the following: VDD V1 V2 V3 V4 V5
(2) System Bus Connection Pins
Name
D7 to D0 SI (D7) SCL (D6) A0 CLS RES C86
I/O
Description
The 8-bit bidirectional data buses to be connected to the 8- or 16- bit standard MCU Data busses. I/O When the serial interface is selected then D7 act as serial data input terminal and D6 act as serial clock input terminal. D5 ~ D0 become high impedance. Usually connected to the low-order bit of the MPU address bus and used to identify the data or a command. I A0=0 : DO to D7 are display control data. A0=1 : DO to D7 are display data.
I I I I I
CLS=1 : internal oscillator enable Input low active. System reset.
CLS=0 : external clock operation mode
CS1, CS2
--
P/S
High level: 68-series MPU interface Low level : 80-series MPU interface This pin select the parallel / serial data input method. P/S = 1 : parallel, P/S = 0 : serial. Input. When CS1 = 0 and CS2 = 1 the chip select become active If the 68-series MPU is connected: Input. Active high. Used as an enable clock input of the 68-series MPU. If the 80-series MPU is connected: Input. Active low. -- The RD signal of the 80-series MPU is entered in this pin. When this signal is kept low, the ST7522 data bus is in the output status. If the 68-series MPU is connected: Input. Used as an input pin of read control signals (if R/W is high) or write control signals (if low). If the 80-series MPU is connected: Input. Active low. The WR signal of the 80-series MPU is entered in this pin. A signal on the data -- bus is fetched at the rising edge of WR signal.
--
E(RD)
--
I
R/W (WR)
--
I
Ver 1.0c
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2002/07/10
ST7522
(3) LCD Driver Circuit Signals
Name
I/O
Description
CL
Input/output. I/O selection M/S = "H" & CLS = "H" Output M/S = "L" & CLS = "H" Input I/O M/S = "X" & CLS = "L" Input This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. Output.
SEGn
O A single level of VDD, V2, V3 and
V5 is selected by the combination of display RAM contents and FR signal. Output. The output pin for LCD common (row) driving. A single level of VDD, V1, V4 and V5 is selected by the combination of common counter output and FR signal. The slave LSI has the reverse common output scan sequence than the master LSI.
COMn COMI
O
O Output. ICON common signals(only use with SEGn)
Input/output. This is the liquid crystal alternating current signal I/O terminal I/O l/O selection M/S = "H"Output M/S = "L"Input
FR
COMS S1~S4
O Output. Static scan line(only use with S1~S4) O Output. Static data (only use with COMS)
Input. The master or slave LSI operation select pin for the ST7522 . Connected to VDD (to select the master LSI operation mode) or Vss (to select the slave LSI operation mode). The slave driver has the reverse common/ segment output scan sequence than the master driver for the convenience of PCB and LCD layout.
M/S
I
M/S High Low M/S High Low
Operating Mode Master Slave
FR Output Input
CL See CLS Input
V1~V5 On Off COMI
Power Supply On Off COMS Pad 75
Internal oscillator See CLS Off S1~S4 Pad 76~79
COM0~COM15 Pad 74~59 Pad 110~125
SEG0~SEG95 Pad 57~110 Pad 74~127
Pad 58 Pad 126
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2002/07/10
ST7522
DESCRIPTION OF FUNCTIONS
The MPU Interface Selecting the Interface Type
With the ST7522 Series chips, data transfers are done through an 8-bit bi-directional data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/S terminal polarity to the "H" or "L" it is possible to select either parallel data input or serial data input as shown in Table 1.
P/S H: Parallel Input L: Serial Input
CS1 CS1 CS1
Table 1 CS2 CS2 CS2 A0 A0 A0
RD RD
WR WR

C86 C86
D7 D7 SI
D6 D6 SCL
D5~D0 D5~D0 High level
High level High level High level
The Parallel Interface
When the parallel interface has been selected (P/S ="H"), then it is possible to connect directly to either an 8080-system MPU or a 6800 Series MPU (as shown in Table 2) by selecting the C86 terminal to either "H" or to "L". Table 2 CS2 CS2 CS2 A0 A0 A0
C86 H: 6800 Series MPU Bus L: 8080 MPU Bus
CS1 CS1 CS1
RD E
WR R/W WR

D7~D0 D7~D0 D7~D0
RD
Moreover, data bus signals are recognized by a combination of A0, RD (E), WR(R/W) signals, as show in Table 3. Table 3 Shared A0 1 1 0 0 6800 Series R/W 1 0 1 0 8080 Series
RD 0 1 0 1
WR 1 0 1 0 Reads the display data Writes the display data Status read Write control data (command)
Function
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ST7522
The Serial Interface
When the serial interface has been selected (P/S = "L") then when the chip is in active state (CS1 = "L" and CS2 = "H") the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. The
A0 input is used to determine whether or the serial data input is display data or command data; when A0 = "H", the data is display data, and when A0 = "L" then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart.
CS1 CS2 SI SCL A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3
Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment.
The Chip Select
The ST7522 Series chips have two chip select terminals: CS1 and CS2. The MPU interface or the serial interface is enabled only when CS1 = "L" and CS2 = "H".
When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, RD , and WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset.
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ST7522
The Accessing the Display Data RAM and the Internal Registers
Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the ST7522 Series. Wait time may not be considered. And, in the ST7522 Series chips, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2.
Writing MPU WR Data Internal Timing N N+1 N+2 N+3
Bus Holder Write Signal
N
N+1
N+2
N+3
Reading WR MPU RD Data N N n n+1
Address Preset Internal Timing Read Signal Column Address Bus Holder Preset N N Increment N+1 n n+1 N+2 n+2
Address Set #n
Dummy Read
Data Read #n
Data Read #n+1
Figure 2
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ST7522
Display Data RAM
The display data RAM is a RAM that stores the dot data for the display. It has a 33 (4 page x 8 bit +1) x 96 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple ST7522 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering).
D0 D1 D2 D3 D4 -
0 1 0 0 1
1 0 0 1 0
1 0 0 1 0
1 0 0 1 0
0 0 0 0 0
COM0 COM1 COM2 COM3 COM4 -
Display data RAM
Liquid crystal display
Figure 3
The Page Address Circuit
As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display data D0 is used.
The Column Addresses
As is shown in Table 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the increment of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 SEG Output ADC set ADC(D0)=0 ADC(D0)=1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized.
Table 4 SEG0 0 95 Column Address Column Address SEG 95 95 0
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ST7522
SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94
D3 D2 D1 D0
Data
D0 D1 D2
............
SEG95 00 95
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
Page Address
SEG COM
COM0 COM1 COM2
c
0
0
0
0
D3 D4 D5 D6 D7 D0 D1 D2
Page 0
COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10
0
0
0
1
D3 D4 D5 D6 D7 D0 D1 D2
Page 1
COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18
0
0
1
0
D3 D4 D5 D6 D7 D0 D1 D2
Page 2
COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26
0
0
1
1
D3 D4 D5 D6 D7
Page 3
COM27 COM28 COM29 COM30 COM31
1
0
0
0
D0 00 01 02 03 04 05 06 07 08
Page 8 87 88 89 90 91 92 93 ............ 94
COMI
ADC=0 COLUMN ADC=1
95
94
93
92
91
90
89
88
87
08
07
06
05
04
03
02
............
Figure 4
Ver 1.0c
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01
2002/07/10
ST7522
Common Timing Generator Circuit
Generates common timing signals and FR frame signals from the CL basic clock. The 1/17 or l/33 duty (for ST7522)can be selected by the Duty Select command. If the l/33 duty is selected for the ST7522 , the l/33 and l/ 17 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode.
Display Data Latch Circuit
This latch stores one line of display data for use by the LCD driver interface circuitry. The output of this latch is controlled by the Display ON/OFF.
FR SIGNAL (Master output) Master Common Slaver Common
0 1 2 3 14 15 0 1
16 17 18
31 32
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ST7522
Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit.
Two-frame alternating current drive waveform
32 CL FR VDD V1 COM0 V4 V5 VDD V1 COM1 V4 V5 RAM Data VDD SEGn V2 V3 V5 33 1 2 3 4 5 6 28 29 30 31 32 33 1 2 3 4 5 6
Figure 5 When multiple ST7522 Series chips are used, the slave chip must be supplied the display timing signals (FR, CL) from the master chip. Table 5 shows the status of the FR and CL signals.
Table 5 Operating Mode FR Master (M/S = "H") The internal oscillator circuit is enabled (CLS = "H") Output The internal oscillator circuit is disabled (CLS = "L") Output Slave (M/S = "L") The internal oscillator circuit is enabled (CLS = "H") Input The internal oscillator circuit is disabled (CLS = "L") Input CL Output Input Input Input
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ST7522
The Liquid Crystal Driver Circuits
These are a 113-channel (ST7522), that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output wave form.
FR
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
COM0
COM1
COM2
SEG0 SEG0 SEG1 SEG2 SEG3 SEG4
SEG1
COM0 to SEG0
COM0 to SEG1
VDD VSS VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5
Figure 6
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ST7522
The Power Supply Circuits
The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, and voltage follower circuits. They are only enabled through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 6 shows the Power Control Set Command 2-bit data control function,.(if Booster is off, than
in master operation.
The power supply circuits can turn the Booster circuits, and the voltage follower circuits ON or OFF independently
the external LCD power supply CAP3 must connect to Vss or external power).
Table 6 Status "1" "0" D2 Booster circuit control bit ON OFF ON D0 Voltage follower circuit control bit OFF The Control Details of Each Bit of the Power Control Set Command Item
The Liquid Crystal Voltage Generator Circuit
The V5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit. 1/6 bias or 1/5 bias for ST7522, can be selected.
VDD-V5 maximum voltage is 7V, VDD-Vcap3 maximum voltage is 7V too.
If VDD < 3.5V , it can use the Booster circuit 2x, The booster voltage can follow the spec. condition (VDD-V5 7V max. voltage.) if VDD >3.5V only use the 1X booster circuit, that can ensure the VDD-V5 voltage 7V. If use the VDD voltage 5V and 2X booster , it's over the spec. operation condition, although adjust the contrast control can make the V5 voltage small than 7V , but the Vcap3 booster voltage already over spec 7V. IC can not guarantee normally work in this condition.
To turn on built-in power(booster/follower) must waiting 200mS to display on for booster/follower stable. Therefore, power off must follow "power off sequence" too.
Power on Power control Booster on Power control Follower on Set Duty/Bias Electronic contrast set Wait time >200mS Display on Display off Display all point on Static indicator off Hardware reset Power off
Power on sequence
Power off sequence
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The Reset Circuit
When the RES input comes to the "L" level, these LSIs return to the default state. Their default states are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Display OFF Static drive is turned OFF. ADC select: Normal (ADC command D0 = 0) Display all point on is select to normal Display normal/reverse is select to normal Power control register: (D2, D0) = (0, 0) Serial interface internal register data clear 1/6 bias is selected 1/17 duty is selected. Read modify write OFF Column address set to Address 0 Page address set to Page 0 Start line set to first line Electronic contrast register = 35H(max:3FH) OSC frequency set = 08H Follower input voltage set =02H Follower amplified ratio = 06H Booster input voltage set = 00H
When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES terminal. After the initialization, each input terminal should be controlled normally. While RES is "L," the oscillator works but the display timing generator stops, and the CL, FR, terminals are fixed to "H." The terminals D0 to D7 are not affected.
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TABLE OF ST7522 INSTRUCTIONS
Instructions
Display on/off Page address set Column address set upper bits
Instruction code
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 Status 0 1 1 0 0 1 1 1 D
Function D=1:Display on D=0:Display off Set MSB 4 bits of column address Set LSB 4 bits of column address
Page address Set display page MSB 4 bits LSB 4 bits 0 0
Column address set lower bits 0 Status read Display data write Display data read Start line set 0 1 1 0
0 Read status Write display data Read display data Determines the RAM display line for COM 0 Display RAM and Segment output correspondence A=1:Reverse A=0:Normal Set LCD display reverse R=1:Reverse R=0:Normal Set display all point on L=1:All on L=0:Normal Column address increment Wr:+1 Rd:+0
Write data Read data 0 Display start address
ADC select
0
1
0
1
0
1
0
0
0
0
A
Display normal/reverse
0
1
0
1
0
1
0
0
1
1
R
Display all point on/off Read/modify/write End Duty select
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 1 1 0
1 1 1 1
0 0 0 0
0 0 1 1
1 0 1 0
0 0 1 0
L 0
0 Clear read/modify/write Select LCD duty U U=1:1/33 duty U=0:1/17 duty Select LCD bias voltage I I=1:1/5 bias I=0:1/6 bias 0 Internal reset B=1:Booster on B=0:Booster off F F=1:Follower on F=0:Follower off
LCD bias set Reset Power control
0 0 0
1 1 1
0 0 0
1 1 0
0 1 0
1 1 1
0 0 0
0 0 1
0 0 B
1 1 0
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TABLE OF ST7522 INSTRUCTIONS(continued)
Instructions Instruction code
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 Electronic contrast set 0 1 0 0 1 OSC Frequency set 0 1 0 0 1 Follower input voltage set 0 1 0 0 Follower amplified ratio 0 1 0 0 1 Booster input voltage set 0 1 0 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 S4 0 0 1 0 1 0 1 0 1 1 Electronic volume 1 0 0 0 1 0 0 0 0 0 0 1 Function
Set contrast by 64 level (V5 fine adjust)
Internal OSC frequency josc josc josc josc adjust 3 2 1 0 1 0 V5 follower input voltage jvref jvref select(V5 coarse adjust) 1 0 0 0
rarb rarb rarb V5 follower amplified ratio 2 1 0 0 0 1 S3 0 0 0 S2 0 0 Booster input voltage select
jbst jbst 1 0 1 0 0
Static indicator on/off static indicator register set
0
1
0 0
S S=1:Indicator on S=0:Indicator off Set the individual indicator S1 on/off
Sleep
Display off + Display all point on + Static indicator off Sleep mode compound command Display off + Display all point on + Static indicator on Stand by mode compound command
Stand by
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Command Description
See the Table of ST7522 instructions. The ST7522 series identifies a data bus using a combination of A0 and R/W (RD or WR) signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed is very high. The busy check is usually not required.
Display ON/FF
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 1
D2 1
D1 1
D0 D
This command turns the display on and off. D=1: Display ON D=0: Display OFF(default)
Set Page Address
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified. The display status is not changed even when the page address is changed.
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 1
D3 A3
D2 A2
D1 A1
D0 A0
This command loads the page address register. A3 0 0 0 0 1 A2 0 0 0 0 0 A1 0 0 1 1 0 A0 0 1 0 1 0 Page 0(default) 1 2 3 8(Icon)
Page mapping see Figure 4.
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Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU continuously, the column address is incremented by I each time it is accessed from the set address. Therefore, the MPU can access to data continuously. The column address stops to be incremented at address 95, and the page address is not changed continuously. A0 0
RD 1
WR 0
D7 0
D6 0
D5 0
D4 0
D3 A3
D2 A2
D1 A1
D0 A0 Low column set
A0 0
RD 1
WR 0
D7 0
D6 0
D5 0
D4 1
D3 A7
D2 A6
D1 A5
D0 A4 High column set
This command loads the column address register. A7 0 0 A6 0 0 A5 0 0 A4 0 0 . . . . 0 1 0 1 1 1 1 1 A3 0 0 A2 0 0 A1 0 0 A0 0 1 Column Address 0(default) 1 . . . . 95
Read Status
A0 0
RD 0
WR 1
D7 0
D6 ADC
D5
D4
D3 0
D2 0
D1 0
D0 0
ON/OFF RESET
Reading the command I/O register (A0=0) yields system status information. The ADC bit indicates the way column addresses are assigned to segment drivers. ADC=1 : Normal. Column address n = segment driver n. ADC=0: Inverted. Column address 95-n = segment driver n. The ON/OFF bit indicates the current status of the display. It is the inverse of the polarity of the display ON/OFF command. ON/OFF=1: Display OFF ON/OFF=0: Display ON The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode, RESET=1: Currently executing reset command. RESET=0: Normal operation
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Write Display Data
A0 1
RD 1
WR 0
D7
D6
D5
D4
D3
D2
D1
D0
Write data
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page, address registers and then increments the column address register by one.
Read Display Data
A0 1
RD 0
WR 1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register. After loading a new address into the column address register one dummy read is required before valid data is obtained.
Start line set
A0 0
RD 1
WR 0
D7 0
D6 1
D5 0
D4
D3
D2
D1
D0
Display start address
Loads the RAM line address of the initial display line, COM 0,into the initial display line register. The RAM display data becomes the top line of the LCD screen. It is followed by the higher number lines in ascending order, corresponding to the duty cycle. The screen can be scrolled using this command by incrementing the line address.(default value="00H")
Select ADC
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 0
D1 0
D0 A
The command selects the relationship between display data RAM column addresses and segment drivers. A=1: SEG0 column address 5FH, ... inverted A=0: SEG0 column address 00H, ... normal (default) This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit Board design. See Figure 4 for a table of segments and column addresses for the two values of D.
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Display Normal/Reverse
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 1
D1 1
D0 R
This command can reverse the lit and unlit display without overwriting the contents of the display data RAM(with ICON). When this is done. the display data RAM contents are maintained . R=1: Reverse R=0: Normal(default)
Display All Points ON/OFF
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 1
D1 0
D0 L
This command makes it possible to force all display points ON regardless of the content of the display data RAM(with ICON). The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. L=1: All display points ON. L=0: Normal(default) Compound command priority follow below table Display all point on Display on Display reverse Display all point on All point black All point white Display all point on Display reverse Display reverse Display reverse All point white Display on Display on Display reverse All point black
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Read-Modify-Write
A0 0
RD 1
WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 0
D0 0
This command defeats column address register auto-increment after data reads. The current contents of the column Address register are saved. The mode remains active until an End command is received. When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write Command. This function can reduce the load of MPU when data change is repeated as a specific display area. *Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column Address Set command cannot be used.
Set page address Set column address
Read-modify-write
Dummy read Read data Write data
Completed? No Yes
End
End
A0 0
RD 1
WR 0
D7 1
D6 1
D5 1
D4 0
D3 1
D2 1
D1 1
D0 0
This command cancels read-modify-write mode and restores the contents of the column address register to their value prior to the receipt of the Read-Modify-Write command.
Returm Column address N N+1 N+2 N+3 N+m N End
Read -modify-write mode set
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Select Duty
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 1
D2 0
D1 0
D0 U
U=1: 1/33 duty cycle (When double chip was be used, then both chip must set duty together ) U=0: 1/17 duty cycle (default)
LCD bias set
A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 0
D1 1
D0 I
I=1:1/5 bias I=0:1/6 bias (default)
Reset
A0 0
RD 1
WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 1
D0 0
the column address, the page address, the start line, the electric volume, and the static indicator are reset, and the read/modify/write mode are released. There is no impact on the display data RAM. The reset operation is performed after the reset command is
This command initializes entered. Their default states are as follows: 1. 2. 3. 4. 5. 6. Column address set to Address 0 Page address set to Page0 Start line set to first line Electronic contrast register = 35H(max=3FH) Static drive is turned OFF Read modify write OFF
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Power control
A0 0
RD 1
WR 0
D7 0
D6 0
D5 1
D4 0
D3 1
D2 B
D1 x
D0 F
B=1: set booster circuit on, which makes Vcap3 has 2 time voltage B=0: set booster circuit off, which make Vcap3 have 1 time voltage only. (default) F=1: set follower circuit on, the V5 electric volume can adjust by internal follower circuit with command set. F=0: set follower circuit off, the V1~V5 must connect to external voltage divider and adjust V5 level by external divider. (default)
B 0 0 1 1
F 0 1 0 1
Step- up circuit Follower circuit Open Open Used Used Open Used Open used
External input voltage Vcap3 connect to V5 V1~V5 connect to external resistor Vcap3 connect to external power supply V1~V5 connect to external resistor -
Booster and follower on/off condition table Note: ensure V5 level stable, that must let |Vcap3-V5| over 0.5V(if panel size over 4.5",the |Vcap3-V5| propose over 0.8V).
VCC GND
VDD VSS V5 Vcap3
VDD
|Vcap3-V5|>0.5V(minimum)
(System side)
(ST7522 Side)
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The Electronic Volume (Double Byte Command)
This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V5. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. That command can operate in master chip for master + slave mode.
The Electronic Volume Mode Set
When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. A0 0
RD 1
WR 0
D7 1
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 1
Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. A0 0
RD 1
WR 0
D7 0
D6 0
D5
D4
D3
D2
D1
D0
Electronic volume
Default value="35H" D7 0 0 D6 0 0 D5 0 0 D4 0 0 . . . . 0 0 1 1 1 1 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 1 V5 level Small . . . . . . Large
The Electronic Volume Register Set Sequence
Electronic volumn mode set
Electronic volumn register set
NO
Change complete YES
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OSC frequency set(Double Byte Command)
This command is designed for frame frequency adjustment, which can provide about 50% variation of frame frequency to avoid the interference with the frequency of daylight lamp in different countries. This command is a two byte command used as a pair with the OSC frequency mode set command and the OSC frequency register set command, and both commands must be issued one after the other.
The OSC frequency mode set
A0 0
RD 1
WR 0
D7 1
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 1
OSC frequency register set
A0 0
RD 1
WR 0
D7 0
D6 0
D5 0
D4 0
D3 Josc3
D2 Josc2
D1 Josc1
D0 Josc0
Default value="08H" Josc3 0 0 Josc2 0 0 . . . . 1 1 1 1 Josc1 0 0 Josc0 0 1 CL Frequency Slow . . . . Fast
Frequency for "OSC frequency set" command
3500 CL frequency[Hz] 3000 2500 2000 1500 1000 500 0 Josc[3,0] CL-1/17 CL-1/33
100
FR frequency[Hz]
80 60 40 20 0
FR-1/17 FR-1/33
Josc[3,0]
Conditions: 1. VDD=3.0V 2. Use internal OSC circuit
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Follower input voltage set(Double Byte Command)
V5 amplifier input voltage can be set by this command, which provide coarse adjustment only. This command needs to be used with the electric volume control command in order to get correct V5 output. This command is a two byte command used as a pair with the follower input voltage mode set command and the follower input voltage register set command, and both commands must be issued one after the other. See the power control explanation for details.
The follower input voltage mode set
A0 0
RD 1
WR 0
D7 1
D6 1
D5 1
D4 1
D3 1
D2 0
D1 0
D0 0
Follower input voltage register set
A0 0
RD 1
WR 0
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 Jvref1
D0 Jvref0
Default value="02H" Jvref1 0 0 1 1 Jvref0 0 1 0 1 V5 input voltage 4/6*VSS 3/6*VSS 2/6*VSS(default) 1/6*VSS
Follower input voltage parameter
Follower amplified ratio
This command sets the V5 voltage internal resistor ratio. that can control V5 level with follower input voltage set command and electric volume command. See the power control explanation for details. A0 0
RD 1
WR 0
D7 0
D6 0
D5 1
D4 0
D3 0
D2 RaRb2
D1 RaRb1
D0 RaRb0
Default value="06H" Rarb2 0 0 0 0 1 1 1 1 Rarb1 Rarb0 V5 amplified ratio
0 0 2 0 1 2.5 1 0 3 1 1 3.5 0 0 4 0 1 4.5 1 0 5(default) 1 1 5.5 Follower amplified ratio parameter
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The V5 level be generate by OPAmp with VDD-Vcap3 power supply, so that V5 level must to be smaller than Vcap3 over -0.5V. Fine adjustment must to used EC[5:0] adjust of Electronic contrast set command. Coarse adjustment must to used jvref[1:0] adjust of Follower input voltage set command.
For V5 voltage level setup formula:
(follower must on of power control command) (used follower input voltage set and amplified ratio command)
Jvref[1,0] Rvref
[1,1] 200K
[1,0] 400K (default)
[0,1] 600K
[0,0] 800K
Rarb2 0 0 0 0 1 1 1 1
Rarb1 0 0 1 1 0 0 1 1
Rarb0 V5 amplified ratio 0 1 0 1 0 1 0 1 2 2.5 3 3.5 4 4.5 5(default) 5.5
[3FH-EC volume] x 20K=REC [ [ Rvref ] x (VSS-VDD) =Vref 1M+REC
Rvref ] x V5 amp ratio x (VSS-VDD) =V5(5% range) 1M+REC
VDD
The value of Vref is not allowed to be lower than 1.2V within the contrast adjustment range.
RaRb[2:0] VDD
VDD Vref Vcap3 V5 F (power control command)
Reference voltage jvref[1:0] Electric volumn EC[5:0]
VSS
7 6 V5
Bias voltage[V]
5 4 3 2 1 0
40 44 48 52 56 12 16 20 24 28 32
V4 V3 V2 V1
Test condition: 1. VDD=3.0V 2. Booster/Follower=Default set 3. Bias=1/6 4. Only master chip
Contrast[5,0]
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60
0
4
8
ST7522
Booster input voltage set (Double Byte Command)
This command is designed to select different level of the input voltage to booster. In 5V application system, it's better to reduce the input voltage of booster to make sure that the output voltage of booster will not be over the specification range of VDD-Vcap3. This command is a two byte command used as a pair with the booster input voltage mode set command and the booster input voltage register set command, and both commands must be issued one after the other. See the power control explanation for details.
The booster input voltage mode set
A0 0
RD 1
WR 0
D7 1
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
Booster input voltage register set.
A0 0
RD 1
WR 0
D7 Jbst1
D6 Jbst0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Default value="00H"
Jbst1 0 0 1 1
Jbst0 0 1 0 1
VSS2 1*VSS(default) 4/5*VSS 3/5*VSS 2/5*VSS
VDD-Vcap3
7
Operating range
5
Booster input voltage parameter
3
For Vcap3 voltage level setup formula:
(booster must on of power control command) (used booster input voltage set command)
1 1 3 5 7
Vcap3=VSS2 x 2
(booster must on of power control command)
VDD
Operating voltage range of Vss and Vcap3 system
Booster VDD
Vcap3
Vcap3=VSS2 x 2 B (power control command)
input voltage jbst[1:0]
VSS2
VSS
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Reference circuit examples:
When used 2x step-up voltage circuit, the "Power control" command must set to 2DH and adjust "Booster input voltage set" command of Vcap3's full range. When used 1x step-up voltage circuit, the "Power control" command must set to 29H; the "Booster input voltage set" command is not action at this operation.
VDD M/S CAP1 Cb CAP2 Cb VDD VSS VDD C1 C2 C3 C4 C5 V1 V2 V3 V4 V5 C1 C2 C3 C4 C5 CAP3 VDD VSS VDD V1 V2 V3 V4 V5 Open CAP2 CAP3 Open CAP1
VDD M/S
VDD=0V VSS=-3V
VDD=0V VSS=-3V
Vcap3=Jbst[1,0] x (VSS-VDD) x 2 2x step-up voltage circuit (Power control=2DH)
Vcap3=(VSS-VDD) x 1 1x step-up voltage circuit (Power control=29H)
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Static Indicator (Double Byte Command)
This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the COMS terminal, and the other is connected to the S1~S4 terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.)
Static Indicator ON/OFF
When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. A0 0
RD 1
WR 0
D7 1
D6 0
D5 1
D4 0
D3 1
D2 1
D1 0
D0 S
S=1: Indicator on S=0: Indicator off (default)
Static Indicator Register Set
This command sets four bits of data into the static indicator register, and is used to set the static indicator into a on/off mode A0 0
RD 1
WR 0
D7 0
D6 0
D5 0
D4 0
D3 S1
D2 S2
D1 S3
D0 S4
the command selection the S1-S4 static indicator on or off. Sn=1: Sn -> on Sn=0: Sn -> Off(default)
Static Indicator Register Set Sequence
Static indicator mode set
Off
On
Static indicator register set
No
Change complete?
Yes
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Power Save (Compound Command)
When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When all static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was ineffect before the power saver mode was initiated, and the MPU is still able to access the display data RAM.
Static indicator off
(Static off only)
Static indicator on
(Static on + Static register set)
Display off Display all point on
Display off Display all point on
Sleep mode
Display on or Display all point off
Stand by mode
Display on or Display all point off
Sleep cancel
Stand by cancel
Sleep Mode
This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment and common drive outputs output a VDD level.
Standby Mode
The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1. The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2. The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. * When the master/slave mode, into Sleep or Standby mode have to at same time.
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Software Example
Condition: 1. VDD=5.0V 2. Use Winbond W78E52-40 at 16MHz crystal(compatible intel 8051 MPU) 3. Use Mater and Slave mode(ST7522D x 2) 4. |VCAP3|=(5x2)x3/5=6V 5. |V5|=[600K/(1M+200K)]x2x5=5V
;Reset
CLR RES ;Reset ST7522D(Master & Slave) CALL DELAY ; SETB RES CALL DELAY ; ;------------------------------------------------------------------------------------------------------------------------------------------------------------------;Initial LCD CLR CS1 ;Enable chip 1(low active) CLR CS2 ;Enable chip 2(low active) MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL CALL MOV CALL A,#11110001B WRINS A,#10001000B WRINS A,#11111000B WRINS A,#00000001B WRINS A,#00100000B WRINS A,#11110000B WRINS A,#10000000B WRINS A,#00101111B WRINS A,#10101001B WRINS A,#10100010B WRINS A,#10000001B WRINS A,#00110101B WRINS DELAY200mS A,#10101111B WRINS . . . . ;OSC frequency set ; ;Frame about 80.6Hz/OSC frequency about 2.6KHz ; ;Follower input voltage set ; ;V5 input voltage=3/6*VSS ; ;Follower amplified ratio ;Ratio=2 ;Booster input voltage set ; ;VSS2=3/5 *VSS ; ;Power control ; ;Duty select ; ;LCD bias set ; ;Electronic contrast set ; ;Contrast register=35H ; ;Delay 200mS for booster & follower stable ;Display on ;
Ver 1.0c
35/45
2002/07/10
ST7522
ABSOLUTE MAXIMUM RATINGS
Characteristics
Power supply voltage LCD driver voltage Input voltage Operating temperature Storage temperature
Symbol
VDD Vcap3 VIN TA TSTO
Value
-0.3 to +7.0 -7.0 to +0.3 -0.3 to VDD+0.3 -40 to +85 -55 to +125
Unit
V V V
DC CHARACTERISTICS
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V
Item
Operating Voltage Step up output voltage Voltage follower circuit operating Voltage V5 accuracy High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Internal Oscillator Oscillator Frequency External Input RECOMMAND
Symbol
VDD Vcap3 V5 V5 VIHC VILC VOHC VOLC ILI ILO RON fOSC
Condition
(Relative to VDD) (Relative to VDD) IOH = -0.5 mA IOL = 0.5 mA VIN = VDD or VSS Ta = 25C (Relative V5 = -6.0 V To VDD) Ta = 25C 1/33Duty
Min.
2.7 -7 -7 -7 0.7 VDD Vss 0.8VDD Vss -1 -1 2 2
Rating Typ. Max.
3.0 5.5 -3.5 -3.5 7 VDD 0.9 VDD 0.2 VDD 2 1 1.6 2.0 3
Unit
V V V % V V uA uA K
Applicable Pin
VDD*1 CAP3 V5 V5 *2 *3 *4 *5 SEGn COMn *6
kHz 3.5
CL
fCL
Ver 1.0c
36/45
2002/07/10
ST7522
* Dynamic Consumption Current, During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. Display Pattern OFF Ta = 25C Vcap3=-6V Item ST7522 Display Pattern Checker Ta = 25C Vcap3=-6V Item ST7522 Symbol IDD Condition VDD=3.0 V, VDD-V5=-5.0V VDD=5.0 V, VDD-V5=-5.0V Min. Rating Typ. 15 40 Max. 20 50 Unit A Notes *7 Symbol IDD Condition VDD=3.0 V, VDD-V5=-5.0V VDD=5.0 V, VDD-V5=-5.0V Min. Rating Typ. 10 35 Max. 15 45 Unit A Notes *7
* Dynamic Consumption Current, During Display, with the Internal Power Supply ON Display Pattern OFF Ta = 25C Vcap3=-6V Item ST7522 Symbol IDD Condition VDD=3.0 V, VDD-V5=-5.0V VDD=5.0 V, VDD-V5=-5.0V Min. Rating Typ. 60 120 Max. 70 130 Unit A Notes *7
Display Pattern Checker Ta = 25C Vcap3=-6V Item ST7522 Symbol IDD Condition VDD=3.0 V, VDD-V5=-5.0V VDD=5.0 V, VDD-V5=-5.0V Min. Rating Typ. 65 130 Max. 80 150 Unit A Notes *7
* Consumption Current at Time of Power Saver Mode, VSS = 0 V, VDD = 3.0 V 10% Ta = 25C Item Sleep mode Standby Mode Symbol IDD IDD Condition Min. Rating Typ. 5 10 Max. 10 15 Unit A Notes -
References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S , and RES terminals. *3 The D0 to D7, FR and CL terminals. *4 The A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, and RES terminals. *5 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, and FR terminals are in a high impedance state. *6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage (3) range. RON = 0.1 V /I (Where I is the current that flows when 0.1 V is applied while the power supply is ON.) *7 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU.

Ver 1.0c
37/45
2002/07/10
ST7522
TIMING CHARACTERISTICS
68 Interface
A0 R/W
tAW6 tAH6
CS1 CS2
tCYC6 tEWHR,tEWHW tEWLR,tEWLW
E
tDS6 tDH6
D0 to D7 (Write)
tACC6
tOH6
D0 to D7 (Read)
Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Read Write Read Write
Signal A0 A0 A0 D0 to D7 D0 to D7 D0 to D7 D0 to D7 E
Symbol
Condition
VDD=2.7 to 4.5V Rating Min. Max. -- -- -- -- -- 90 1100 -- -- -- --
(Ta = -40 to 85C ) VDD=4.5 to 5.5V Rating Units Min. 10 10 3500 25 10 -- -- 160 160 140 1200 Max. -- -- -- -- -- 60 1100 -- -- -- -- ns ns ns
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW
-- -- --
10 25 4400 25 10 -- -- 260 260 200 2300
CL = 100 pF
ns
--
ns
Enable L pulse time
E
--
ns
*1 All timing is specified using 20% and 80% of VDD as the reference. *2 tEWLW and tEWLR are specified as the overlap between CS1 being "L" (CS2 = "H") and E.
Ver 1.0c
38/45
2002/07/10
ST7522
80 Interface
A0
tAW8 tAH8
CS1 CS2
tCYC8 tCCLR,tCCLW tCCHR,tCCHW
WR,RD
tDS8 tDH8
D0 to D7 (Write)
tACC8
tOH8
D0 to D7 (Read)
Item Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD ) Control H pulse width (WR) Control H pulse width (RD ) Data setup time Address hold time
Signal A0 A0
Symbol
Condition -- --
VDD=2.7 to 4.5V Rating Min. Max. -- -- -- -- -- -- -- -- -- 70 1200 10 10 3400 350 530
(Ta = -40 to 85C ) VDD=4.5 to 5.5V Rating Units Min. 10 10 1300 160 200 1100 530 10 10 -- -- Max. -- -- -- -- -- ns -- -- -- -- 70 1100 ns ns ns ns
tAH8 tAW8 tCYC8 tCCLW tCCLR
--
WR
--
RD
--
--
WR
--
--
RD
--
tCCHW tCCHR tDS8 tDH8 tACC8 tOH8
-- CL = 100 pF
1100 730 25 10 -- --
--
--
D0 to D7 D0 to D7
--
RD access time
Output disable time
*1 All timing is specified using 20% and 80% of VDD as the reference. *2 tCCLW and tCCLR are specified as the overlap between CS1 being "L" (CS2 = "H") and WR and RD being at the "L" level.
Ver 1.0c
39/45
2002/07/10
ST7522
Serial Interface
tCSS tCSH
CS1 CS2
tSAS
tSAH
A0
tSCYC tSLW tSHW
SCL
tSDS
tSDH
SI
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
Signal
Symbol
Condition
VDD=2.7 to 4.5V Rating Min. Max. -- -- -- -- -- -- -- -- --
(Ta = -40 to 85C ) VDD=4.5 to 5.5V Rating Units Min. Max. 400 300 120 0 100 0 100 40 1000 -- -- -- -- -- -- -- -- -- ns ns ns ns
tSCYC
SCL
500 -- 100 200 -- -- -- 0 100 0 120 60 2200
tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
A0 SI CS
*1 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.0c
40/45
2002/07/10
ST7522
Reset Timing
tRW RES tR Internal status During reset
Figure 41
Reset complete
Table 36 Item Reset time Reset "L" pulse width Signal -- RES Symbol Condition -- -- Rating Min. -- 0.2 Typ. 1 1 Max. 100 -- Units s s
tR tRW
*1 When double chip was be used, then the duty set command must be set between the tR
Ver 1.0c
41/45
2002/07/10
ST7522
I/O PAD CONFIGURATION
VDD VDD Pull up control VDD VDD VDD
I/O PAD
I/O PAD
VSS VDD VSS P MOS VSS
VSS VDD P MOS
N MOS
N MOS
VSS
VSS
I/O PAD:D0,D1,D2,D3,D4,D5
VDD VDD Input PAD
I/O PAD:D6,D7,FR,CL
VSS VSS
Input PAD: RES,P/S,/CS1,CS2,CLS, E(/RD),R/W(/WR),A0,C86,M/S
D0~D5 into pull up mode when P/S set to VSS(Serial interface), but P/S set to VDD(Parallel interface), D0~D5 will be without pull up MOS connected.
Ver 1.0c
42/45
2002/07/10
ST7522
THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7522 Series can be connected to either 80x86 Series MPUs or to 68000 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7522 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7522 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs
VDD VCC VDD A0 P/S CS1 CS2 D0 to D7 RD WR RES VSS C86 ST7522
A0 A1 to A7 IORQ D0 to D7 RD WR RES GND
MPU
DECODER
RESET
(2) 6800 Series MPUs
VDD A0 A1 to A15 VMA D0 to D7 E R/W RES GND VCC VDD A0 P/S CS1 CS2 D0 to D7 E R/W RES VSS C86 ST7522
MPU
DECODER
RESET
(3) Using the Serial Interface
VDD VCC A0 A1 to A7 PORTA PORTB RES GND RESET DECODER VDD A0 P/S CS1 CS2 D0 to D5 SI SCL RES VSS C86 ST7522
Ver 1.0c
MPU
43/45
2002/07/10
1. 2. 3.
44 43 42 41 40 39 38 3 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56
SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73
44 43 42 41 40 39 38 3 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
COMS S1 S2 S3 S4 P/S CL VSS D0 D1 D2 D3 D4 D5 D6 D7 /CS1 CS2 E A0 R/W VDD C86 RES CLS FR V1 V4 V3 M/S V5 V2 CAP1 CAP2 CAP3 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88
75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
VDD
C7 C6 C2 C5 C3
VDD VDD
VDD
VSS
75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
COMS S1 S2 S3 S4 P/S CL VSS D0 D1 D2 D3 D4 D5 D6 D7 /CS1 CS2 E A0 R/W VDD C86 RES CLS FR V1 V4 V3 M/S V5 V2 CAP1 CAP2 CAP3 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
APPLICATION (Master & Slave Mode)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Notice: Slave chip's common & segment pin had changed follow "PIN DESCRIPTION" table
2002/07/10
VSS VDD Vout A0 R/W E D0 D1 D2 D3 D4 D5 D6 D7 CS1 CS2 RES
CL V1 V2 V3 V4 V5
Ver 1.0c
Condition:
ST7522
LCD 33 x 160 dots
2 time booster internal follower internal OSC frequency
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COMI COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
ST7522 Master
SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118
ST7522 Slave
SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 COMI COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8
148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118
44/45
Capacitor C1 C2 C3 C4 C5 C6 C7
J1
3 2 1
C4 C1 Panel size
P/S
J2 Viewing area=3.0" 2.2uF 2.2uF 1uF 2.2uF 2.2uF 2.2uF 2.2uF Viewing area=4.5" 4.7uF 4.7uF 2.2uF 4.7uF 4.7uF 2.2u~4.7uF 2.2u~4.7uF
3 2 1
C86
J3
3 2 1
CLS
ST7522
APPLICATION(Only use master mode)
Resemble ST7066U+ST7065C (2 line x 16 word with 14 pin assign application)
condition:
1. 2. 3. 4. 68 interface 2 time booster internal follower internal OSC frequency
LCD 17 x 96 dots
Panel size Capacitor C1 C2 C3 C4 C5 C6 C7
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
Viewing area=3.0" 2.2uF 2.2uF 1uF 2.2uF 2.2uF 2.2uF 2.2uF
Viewing area=4.5" 4.7uF 4.7uF 2.2uF 4.7uF 4.7uF 2.2u~4.7uF 2.2u~4.7uF
VDD
75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 COMS S1 S2 S3 S4 P/S CL VSS D0 D1 D2 D3 D4 D5 D6 D7 /CS1 CS2 E A0 R/W VDD C86 RES CLS FR V1 V4 V3 M/S V5 V2 CAP1 CAP2 CAP3 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88
SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COMI COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
ST7522
VSS VDD RES A0 R/W E D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
C6
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56
44 43 42 41 40 39 38 3 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87
C7 C1 C4 C3 C5 C2
148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118
Ver 1.0c
45/45
2002/07/10

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